Dorsavi Commences Energy Efficiency Study for Next-Gen RRAM AI Hardware

dorsaVi targets energy efficiency benchmark for next-gen ultra-edge hardware

dorsaVi Limited (ASX: DVL) has commenced targeted electrical measurements of its engineered RRAM structures to quantify the energy required to update memory states, marking a foundational benchmarking step in the company’s RRAM-CMOS hardware development pathway. The results are intended to feed into subsequent evaluation using the company’s RRAM Validation Chip, covering array-level operation, Compute-in-Memory (CIM) and CMOS-integration assessment.

What is RRAM and why does energy efficiency matter at the ultra-edge?

Resistive Random-Access Memory (RRAM) is a memory technology that stores data by switching between electrical resistance states. Unlike conventional memory architectures that transfer raw data to a central or cloud processor for interpretation, ultra-edge systems aim to retain and act on data locally, at or near the point of sensing, without cloud dependency.

This distinction matters in compact Physical AI systems such as robots, wearables, and autonomous machines, where power, space and thermal budgets are constrained. When memory is updated frequently alongside sensing and local processing functions, the energy cost of each state update becomes a relevant design consideration. Lower-energy RRAM updates may preserve more of the available local power budget for other functions.

RRAM serves as the memory component within a broader architecture. The sensing-to-response chain operates broadly as follows:

1. Sense — physical data is captured at the sensor
2. Retain (RRAM) — selected data is held locally in memory
3. Interpret locally — CMOS logic and, in future, CIM or neuromorphic functions process the retained data
4. Respond — the system acts on that local interpretation

RRAM does not operate as a standalone solution. Its role is as a potential enabling memory technology within a broader integrated hardware architecture.

Physical AI applications driving the commercial opportunity

Markets where local memory and processing may matter

The announcement identifies several illustrative Physical AI application verticals where near-sensor memory and processing may become increasingly relevant:

• Advanced robotics — humanoid robots, robotic arms and grippers handling multiple contact points
• Autonomous vehicles and mobile machines — continuous perception under tight energy constraints
• Industrial automation — real-time response to material variation and alignment
• Adaptive wearables — body-worn sensing of movement and load
• Drones and aerial systems — flight decisions within compact power budgets
• Medical and surgical robotics — precise motion under strict operational limits

Each of these markets shares a common constraint: tight space, power and thermal limits that make efficient near-sensor memory increasingly relevant. These are reference applications only and do not represent dorsaVi-developed systems.

Advanced humanoid robotic hands — an illustrative use case

Advanced robotic hands illustrate the ultra-edge challenge at a system level. Such hands may incorporate tactile sensing across articulated fingers and the palm, generating pressure, contact, force and slip data across multiple points simultaneously.

Unlike conventional industrial grippers designed for repeatable movements in structured environments, next-generation hands may need to handle irregular parcels, flexible materials, delicate components and everyday objects requiring continuous adaptation. In prospective architectures, RRAM may serve as a potential enabling memory layer, retaining selected tactile context close to where that data is generated. Interpretation and coordinated response would rely on surrounding CMOS logic and potentially future CIM or neuromorphic functions.

This use case is illustrative and prospective. It does not represent a dorsaVi-developed product or system.

Mathew Regan, Group Chief Executive Officer

“The physical world creates a different challenge for AI. It is not enough for a machine to identify an object. It must be able to understand what is happening when it touches that object. Advanced robotic hands are a powerful reference application because they show why memory, processing and energy efficiency need to move close to the point of contact. Our study is focused on the energy efficiency of our RRAM structures and how that may support the next generation of ultra-edge hardware.”

Development pathway and what comes next

The current assessment is focused on generating device-level electrical measurements of RRAM state-update energy to establish an initial performance benchmark. Importantly, this study is not designed to determine the full power consumption of a broader Physical AI platform, which also includes sensing, CMOS logic, communications, actuation and other components.

Results from this benchmarking work are intended to provide an input for subsequent evaluation using dorsaVi’s RRAM Validation Chip, which will extend the program towards array-level operation, CMOS integration and future Compute-in-Memory assessment, alongside further reliability and workload-level evaluation.

Alongside energy efficiency, thermal stability validation has been a parallel focus for the RRAM program, with testing against AEC-Q100 automotive-grade methodology confirming fully reversible cell behaviour at temperatures up to 150°C across all test points.

The table below outlines the current status of key milestones within the RRAM-CMOS development pathway:

Subject to further validation, lower-energy RRAM updates could be a useful characteristic for future local or near-sensor memory architectures. Any system-level impact will depend on the eventual array design, associated CMOS, integration approach, compute architecture and workload. For dorsaVi, energy-efficient RRAM remains a potential building block within its broader RRAM-CMOS and future CIM hardware pathway.

For investors wanting to understand the architecture in greater detail, our full explainer on the RRAM-CMOS validation chip design covers the three integrated capabilities being tested simultaneously: write-and-verify circuitry, compute-in-memory operation across up to 64 inputs, and BEOL integration on commercial CMOS wafers sourced through TSMC.

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