dorsaVi begins silicon manufacturing of its first RRAM validation chip
dorsaVi (ASX: DVL) has commenced the tape-out of its first RRAM-CMOS validation chip with tier-one semiconductor partners, moving the program from completed design into physical silicon manufacturing.
The step is designed to validate the company’s RRAM platform for future AI, robotics, EV and wearable applications. It follows the recently finalised RRAM-CMOS validation chip design, first detailed in the company’s ASX announcement dated 28 January 2026.
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Key highlights of the tape-out milestone
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Tape-out commenced with tier-one semiconductor partners, progressing the program from a finalised design package into staged silicon implementation.
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Advances the 22-nm RRAM development program from design completion toward fabrication and wafer-level testing.
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Implementation uses commercial CMOS front-end wafers sourced through TSMC, followed by partner-led BEOL and RRAM integration.
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Targets rising edge-AI demand for local, low-power, non-volatile memory.
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Designed to generate critical silicon validation data to guide RRAM integration, circuit optimisation and manufacturing refinement.
What tape-out means, and why it matters
Tape-out is the process by which a finalised integrated circuit design package is prepared for physical manufacturing. It marks the transition from design to fabrication, proving the architecture is ready for standard commercial foundry conditions.
The milestone is significant because it moves the validation chip out of the design stage and into the implementation flow required to produce testable silicon. This step generates the physical data needed before any commercial scaling.
The RRAM-CMOS validation chip design integrates three capabilities simultaneously: self-checking write-and-verify circuitry, compute-in-memory operation accumulating across up to 64 inputs, and BEOL integration on commercial CMOS wafers sourced through TSMC.
At the heart of the platform is RRAM, a type of non-volatile, low-power memory that retains data without a constant power supply. The chip also integrates Compute-in-Memory (CIM) structures, an approach where the same physical layer that stores data can also perform calculations locally, avoiding the constant shuttling of data between memory and a separate processor.
The three purposes of the validation chip
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Validation of advanced memory features — confirming the RRAM memory array, dedicated write-and-verify circuitry and Compute-in-Memory structures operate together under physical silicon conditions.
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Opens the pathway to high-value applications — progressing toward embedding validated silicon into target platforms across exoskeletons, robotics, defence and industrial AI.
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Scalable manufacturing process — using commercial CMOS front-end wafers and integrating the RRAM stack into existing back-end-of-line (BEOL) flows, drawing on established foundry infrastructure.
Two pathways to meet global AI memory demand
Because the technology is designed for standard commercial CMOS processes, dorsaVi has outlined two potential commercialisation pathways.
The first would be embedding the technology directly into end-devices. The second would be working alongside foundries and fabless chip makers to develop specialised chips for targeted applications.
Both are intended to be accessible without new manufacturing investment, which the company suggests could make the technology practical for adoption across robotics, electric vehicles, exoskeletons and industrial AI.
High-value markets targeted by dorsaVi’s RRAM
The validation work supports the company’s broader ultra-edge intelligence roadmap, where local memory, low-power processing and on-device decision-making are expected to be important for future sensing and hardware platforms.
For readers wanting to understand how the platform holds up under real operating conditions, our full explainer on thermal stability validated at 150 degrees C covers the AEC-Q100 methodology and what reversible cell behaviour at extreme temperatures means for defence, robotics, and industrial deployment.
| Market | Specific application | How RRAM benefits it |
|---|---|---|
| Smart Exoskeletons | EMG-driven intent recognition nodes | Fast writes inside the control loop; non-volatile storage of each user’s personalised baseline without cloud dependency |
| Robotics | Joint position and torque controllers | Non-volatile memory survives power cycles, so the limb wakes up calibrated without re-homing |
| Defence | Autonomous edge sensing platforms | Local inference without connectivity; low power draw extends operational endurance in the field |
| Industrial AI | On-device model inference | Model weights held non-volatile and adjacent to compute; eliminates power-hungry data reload cycles |
| Medical & Wearables | Continuous biosignal monitoring | Always-on, low-power memory retains patient baselines locally, removing reliance on external processing |
CEO commentary
Mathew Regan, Group Chief Executive Officer
“Commencing the tape-out of our first RRAM test-chip is a significant milestone for the program. It confirms that our RRAM architecture is manufacturable under standard commercial foundry conditions and gives us the physical silicon we need to validate performance and refine the technology. We are focused on executing this next phase of testing and using the results to advance the program toward commercial scaling.”
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What comes next
The validation chip follows a staged silicon implementation flow. It begins with commercial CMOS front-end wafers sourced through TSMC, followed by partner-led BEOL and RRAM integration, before wafer-level electrical testing.
This staged approach allows dorsaVi and its partners to evaluate RRAM integration on a commercial CMOS foundation while preserving flexibility for process learning and future node migration. The data generated is expected to inform future optimisation of the platform and support the subsequent 22-nm implementation pathway. The company has not disclosed a completion timeline.
The program sits alongside dorsaVi’s established wearable sensor business across its Workplace and Clinical markets, forming part of its stated ambition to build the hardware foundations of “ultra-edge intelligence.”
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