Why the AI Spending Boom Masks Two Memory Pricing Risks

HSBC’s Chief Multi-Asset Strategist Max Kettner has described the near-term earnings bar for US technology stocks as “straightforward to exceed.” The assessment, delivered against a backdrop of deep order backlogs and firm hyperscaler capital expenditure, captures a near-consensus view across the semiconductor complex: the AI spending boom is intact, and the next quarter’s numbers are unlikely to disappoint. But embedded in the same HSBC note that offers near-term reassurance are two longer-dated structural warnings that most coverage has glossed over, and both converge on the same pressure point: memory pricing power.

What follows unpacks those two risks, explains the mechanisms through which efficiency-driven demand compression and China’s commercial DDR5 ramp could eventually reshape the semiconductor earnings picture, and offers a framework for investors holding both the constructive near-term thesis and the medium-term structural question simultaneously.

The near-term case is solid, and that is exactly what makes the longer view worth watching

HSBC’s constructive near-term read is grounded in observable data, not sentiment. Market consensus projects only a modest quarter-over-quarter decline in US earnings per share for Q2, a bar Kettner views as manageable and likely to be beaten.

HSBC characterised the upcoming Q2 earnings bar for US technology stocks as “straightforward to exceed,” framing near-term earnings expectations as a potential upside catalyst rather than a meaningful downside risk.

The demand signals reinforce the call. Texas Instruments guided Q2 2026 revenue at $5.00 billion to $5.40 billion in its April 2026 earnings release, confirming continued data-centre recovery. Three near-term demand supports anchor the thesis:

The current memory chip supercycle differs from every previous DRAM upcycle in one critical respect: AI data centre operators now account for an estimated 70% of total memory shipment volumes, meaning the demand anchor is no longer consumer electronics or enterprise servers but the concentrated capex decisions of a handful of hyperscalers whose spending commitments extend well beyond a single quarter.

• Substantial order backlogs across AI-exposed semiconductor suppliers, making a near-term spending deceleration unlikely
• Firm hyperscaler capex commitments through the current infrastructure buildout cycle
• Data-centre resilience visible in supplier guidance, with Texas Instruments’ Q2 range consistent with sustained demand

None of this is contested. The near-term AI infrastructure cycle has the order books, the capex commitments, and the earnings momentum to carry through the next several quarters. That is precisely what makes the structural risks forming at the edges of the frame worth examining now, before the consensus is forced to reckon with them.

What HSBC actually flagged, and why the framing matters

Kettner’s note identified two longer-dated structural risks for technology and memory-exposed equities. They are not equivalent, and they do not operate through the same channel. One is a demand-side concern; the other is a supply-side concern. Their significance lies in where they converge.

HSBC framed both risks as explicitly longer-dated, not imminent threats to the current earnings cycle. The distinction matters. These are not reasons to sell semiconductor exposure today. They are reasons to understand the mechanism through which the current pricing cycle could eventually compress, because both risks converge on the same outcome: downward pressure on DDR5 and DRAM pricing power.

How AI efficiency improvements threaten the memory pricing cycle

DDR5 pricing has shown strength through April 2026, according to DRAMeXchange, TrendForce, and Silicon Data, reflecting tight supply conditions and sustained AI-server demand. That pricing environment is the baseline against which the efficiency headwind should be understood.

DRAM supply constraints extend well beyond the DDR5 segment the current pricing discussion focuses on: HBM inventory across the three major producers sits at roughly 3-4 weeks industry-wide, all three suppliers are fully sold out through 2026, and the new capacity committed by Micron and SK Hynix will not reach meaningful output until 2027-2028, reinforcing the near-term pricing floor that makes the efficiency and China risks longer-dated rather than immediate.

The causal chain runs as follows:

1. AI model efficiency improves through software optimisation and architecture design, reducing the compute and memory required per inference workload
2. Memory intensity per unit of AI output declines as fewer DRAM modules are needed to serve the same throughput
3. Aggregate demand growth for memory moderates, even if the number of AI workloads continues to increase
4. Pricing power compresses as suppliers face a demand mix that requires less memory per deployment cycle

Industry commentary through 2025 to 2026 has described a shift toward an efficiency-focused phase in AI development, where software optimisation and model improvements could change the hardware demand mix for inference workloads.

HSBC’s framing positions this as a structural pattern, not a speculative thesis. Efficiency-related gains at the model and hardware architecture level could ultimately constrain the pricing power currently enjoyed by memory suppliers. The timing remains uncertain, but the direction of the pressure is not. Investors in memory-exposed equities who recognise that current DDR5 pricing strength is partly a function of AI hardware intensity, not supply discipline alone, hold a more complete view of where the cycle could turn.

The Stanford HAI AI Index findings on model efficiency document a generational shift toward smaller, optimised models that achieve comparable performance to earlier large-scale architectures while requiring significantly fewer computing resources, providing an empirical grounding for the memory intensity compression thesis.

China’s DDR5 ramp is no longer a future risk, it is a present one

ChangXin Memory Technologies (CXMT) has moved beyond qualification into commercial delivery. The capability data is specific.

• 24Gb/16nm-class DDR5 parts are in the commercial supply chain as of mid-2026
• Yield performance has reached 80%+, according to TechInsights and the South China Morning Post (May 2026)
• Chinese memory module makers are accelerating consumer and enterprise DDR5 product releases using domestically produced chips

CXMT remains roughly one generation behind Samsung, SK Hynix, and Micron on density. The technology gap, however, has narrowed materially since 2025, and the trajectory suggests continued progress.

Incumbent memory suppliers absorbed that repricing rapidly in equity markets: Micron, Sandisk, and SK Hynix posted combined gains exceeding 250% over the 30 days ending May 12, 2026, a move driven by sold-out HBM capacity and early signals from US-China trade discussions that tool-access waivers for CXMT and YMTC were unlikely to materialise in the near term.

The pricing mechanism

The competitive threat operates through supply-side arithmetic. As Chinese domestic DDR5 production scales, it adds incremental supply to a market where pricing has been supported by the discipline of three dominant suppliers. Even if global demand remains firm, the introduction of a fourth significant source of DDR5 supply at competitive price points creates contract pricing pressure that incumbents cannot fully offset through product differentiation alone.

HSBC specifically cited China’s growing competitive position in the DDR5 market as a longer-horizon concern. The CXMT ramp suggests investors in incumbent memory suppliers should begin incorporating a supply-side pricing headwind into their medium-term models, even if the impact remains modest through the balance of 2026.

What the two-speed thesis means for tech equity positioning

The demand-side risk (efficiency compression) and the supply-side risk (China’s DDR5 ramp) require separate analytical treatment because they operate on different timelines and affect different parts of the supply chain with different intensity.

The semiconductor earnings consensus remains broadly constructive through 2026 for AI-server and high-bandwidth memory exposed firms. HSBC’s framework does not challenge that near-term view. It asks investors to hold a second question alongside it: under what conditions do the longer-dated risks begin to pull forward?

Three monitoring signals can help answer that question:

Investors wanting to pressure-test the incumbent supplier valuation case before incorporating the structural risks discussed here will find our deep-dive into the AI memory bull thesis stress test, which examines KB Securities’ foundry-style contracting assumptions, the three compounding HBM supply constraints, and the specific valuation starting point risks for SK Hynix and Samsung that become material if ASP projections miss.

• DDR5 contract price trend direction: sustained flattening or sequential declines in DRAMeXchange and TrendForce data would suggest the pricing cycle is maturing
• CXMT production volume updates: rising output figures and new product category entries would confirm the supply-side pressure is scaling
• Hyperscaler AI capex guidance commentary: any shift in language toward efficiency optimisation over capacity expansion on quarterly earnings calls would signal the demand-side thesis is materialising

The AI spending boom is real, but memory markets have their own memory

The near-term AI capex thesis is well-supported. Order backlogs are deep, hyperscaler commitments are firm, and the Q2 earnings bar sits at a level HSBC considers straightforward to clear. None of that is being dismissed.

What HSBC’s note adds is the structural question that sits behind the earnings consensus. Efficiency compression on the demand side and China’s supply ramp are two independent forces, originating from different parts of the global technology ecosystem, converging on the same pressure point: DDR5 and DRAM pricing power. Neither risk is imminent. Both are observable.

HSBC characterised both efficiency-driven memory price compression and China’s growing DDR5 competitive position as longer-dated structural risks, explicitly distinguishing them from near-term earnings concerns.

Semiconductor cycles have consistently rewarded investors who kept the medium-term picture in peripheral vision while the near-term thesis remained strong. The question is not whether these risks exist. The CXMT commercial ramp and industry commentary on AI efficiency have answered that. The question is when they become material enough to affect valuations, and that question requires active monitoring of DDR5 contract pricing, CXMT output data, and hyperscaler capex language, rather than passive confidence in the current cycle’s momentum.

This article is for informational purposes only and should not be considered financial advice. Investors should conduct their own research and consult with financial professionals before making investment decisions. These forward-looking statements regarding memory pricing and competitive dynamics are subject to change based on market developments and company performance.