Nanoveu Ltd Secures US Patent for AI Object Detection Chip Circuitry

Nanoveu secures US patent for AI object detection silicon built into next-gen ECS-DoT chip

Nanoveu Limited (ASX: NVU) has confirmed that US Patent No. 12,651,452 B2 has been granted by the United States Patent and Trademark Office (USPTO), covering dedicated accelerator circuitry for AI object detection built into its next-generation ECS-DoT chip.

The patent covers dedicated accelerator circuitry for non-maximum suppression, a mandatory final stage in AI object detection. It is assigned to Nanyang Technological University, Singapore (NTU) and exclusively licensed to EMASS, Nanoveu’s ultra-low-power semiconductor division.

The patented innovation was co-invented by Dr Mohamed Sabry, the founder of EMASS, who is employed at NTU. The grant protects the silicon efficiency behind ECS-DoT ahead of its commercial rollout, strengthening the competitive position of Nanoveu’s core semiconductor architecture.

What the granted patent protects

Non-maximum suppression is the final stage in every AI object detection pipeline. It is conventionally run in software, where it consumes a disproportionate share of inference time and energy.

The patented innovation executes the same function in purpose-built silicon, removing a structural bottleneck in edge vision. In peer-reviewed research underlying the patent, a hardware implementation of the approach reported:

• Speedups of up to 75× over a software implementation of the same algorithm

• 13.4× over the prior state-of-the-art hardware accelerator

• Comparable detection accuracy at full-HD input resolutions

These figures are modelled outcomes from peer-reviewed research and do not constitute physical test results.

The patented mechanism is implemented as a dedicated hardware acceleration module in the BLE-enabled next-generation 16nm ECS-DoT, which entered fabrication at TSMC in January 2026.

Dr Mohamed Sabry, EMASS founder

“Object detection is where edge vision silicon wins or loses on power, and non-maximum suppression is the stage conventionally left to software. This patent covers executing it in dedicated hardware instead, and that module is built into our next generation 16nm silicon. The exclusive licence puts that mechanism in EMASS’s hands, and we intend to follow the same path from research to protected silicon across voice, motion and sensor fusion.”

Why object detection efficiency matters for edge AI

Edge AI refers to processing data directly on a device rather than sending it to the cloud. Vision is a core edge AI workload, and efficient object detection is what makes always-on operation practical for battery-powered devices.

Power efficiency is the competitive battleground for edge silicon. The less energy a chip needs to run continuous vision tasks, the longer a device can operate without recharging, and the more viable always-on sensing becomes in compact hardware.

ECS-DoT energy efficiency benchmarks presented at the Pitt Street Research Semiconductor Conference 2026 placed the chip at up to 20x the efficiency of competing solutions per MLCommons 2025 data, contextualising why dedicated hardware acceleration for workloads like non-maximum suppression is central to the platform’s competitive positioning.

For investors, this is the “so what”: the patent supports ECS-DoT’s positioning across target applications including smart cameras and doorbells, wearables such as smart glasses and AR/VR headsets, drones, and automotive sensing.

Building a broader IP portfolio

This grant protects one workload within a substantially larger surface. ECS-DoT processes vision, audio and sensor data across the Company’s target verticals, meaning object detection is only part of the picture.

Nanoveu intends to pursue further filings across additional workloads. Planned and previously flagged filings include:

• Voice workloads

• Motion workloads

• Sensor fusion workloads

• Patent families previously flagged covering the Company’s drone energy optimisation and flight control technology

The strategic significance for investors is the “research to protected silicon” pathway, which is intended to build a defensible IP position around EMASS’s core architecture.

What it means for Nanoveu investors

IP protection strengthens the commercial value of ECS-DoT ahead of its market rollout and reinforces EMASS’s differentiation on ultra-low-power performance. Securing dedicated silicon protection for a core workload adds a layer of defensibility around the chip’s efficiency advantage.

Next milestones for investors to watch include additional patent filings across voice, motion and sensor fusion workloads, alongside progression of the 16nm ECS-DoT from fabrication toward commercial availability. The company has confirmed only that fabrication commenced at TSMC in January 2026, and no commercial launch date has been disclosed.

EMASS operates as Nanoveu’s fabless semiconductor division, specialising in ultra-low-power, AI-enabled system-on-chip solutions targeting always-on sensing and intelligent processing at the edge. This patent grant sits within that broader strategy of protecting the silicon architecture underpinning its edge AI ambitions.

For readers wanting to understand how Nanoveu is funding ECS-DoT’s path from fabrication to commercial availability, our detailed coverage of the $7.5M capital raise outlines the dual-track strategy spanning TSMC manufacturing progression and live drone field trials, including the partnership arrangements with Arrow Electronics and Semtech supporting market entry.

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