dorsaVi clears critical CMOS fabrication milestone on RRAM validation chip
dorsaVi (ASX: DVL) has completed front-end-of-line (FEOL) and middle-of-line (MOL) CMOS fabrication for its first RRAM-CMOS validation chip, using TSMC’s established CMOS process.
The achievement completes Phases 1 and 2 of the validation chip build, with the dorsaVi–NTU RRAM development program now advancing into Phase 3, the proprietary back-end-of-line (BEOL) RRAM integration sequence.
With the foundational silicon platform in place, the program moves a step closer to an electrically testable chip built around dorsaVi’s proprietary RRAM architecture.
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What was completed, and what comes next
The front-end-of-line contains the transistor layer of the validation chip, while the middle-of-line provides the local interconnects connecting those devices. Together, they form the foundational CMOS platform required for subsequent RRAM integration.
Fabricating these layers through TSMC’s established CMOS process provides what the Company describes as a “proven foundation” for the validation chip. This allows the next development phase to focus purely on the RRAM-specific integration steps within the back-end-of-line.
| Phase | Stage | What it does | Status |
|---|---|---|---|
| Phase 1 | CMOS front-end-of-line (transistor) | The base transistor layer | Complete |
| Phase 2 | Middle-of-line interconnects | Foundational local wiring | Complete |
| Phase 3 | Back-end-of-line RRAM integration | RRAM deposition, etching & subsequent metal/interconnects | To follow |
| Phase 4 | Post-fabrication electrical testing | Wafer electrical validation | To follow |
Phase 3 encompasses a defined BEOL sequence:
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Fabrication of the engineered via structure forming the RRAM bottom electrode
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Deposition of the proprietary RRAM material stack
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RRAM cell etching
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Subsequent metal lines and interconnect fabrication (BEOL) toward electrical testing
Why RRAM and edge memory matter for Physical AI
RRAM, or resistive RAM, is a low-power, non-volatile memory. That combination is central to what dorsaVi is targeting.
The announcement points to a shift in where computing happens. Physical AI systems increasingly need processing and memory to sit at the “ultra-edge,” close to the sensor, rather than in the cloud.
Power and memory efficiency are the binding constraints on what these edge devices can do locally, and this is exactly what dorsaVi’s RRAM technology is targeted at. For investors, progress on the validation chip advances the roadmap toward memory that supports this local processing.
Thermal validation at 150 degrees confirmed fully reversible, predictable RRAM cell behaviour with zero permanent degradation, a result structured against AEC-Q100 automotive-grade methodology that underpins the reliability credentials the platform carries into this fabrication phase.
The Company identifies several target Physical AI markets:
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Robotics
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Exoskeletons
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Autonomous vehicles
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Drones
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Other Physical AI and autonomous systems platforms
The investment angle: positioning in high-value edge hardware
The milestone connects to dorsaVi’s broader strategy of building the hardware foundations of the ultra-edge through strategic investments in neuromorphic computing and RRAM memory technology.
Management framed the program as advancing “in line with our project plan.” Fabricating these layers through TSMC’s established CMOS process provides a proven foundation for the validation chip, allowing the next phase to focus on RRAM-specific integration steps.
This ultra-edge strategy sits on top of dorsaVi’s existing commercial footprint, an established wearable sensor business spanning workplace and clinical markets with users including Boeing, Caterpillar (US), Coles, Woolworths and BHP.
For investors exploring how the validated silicon feeds into a broader commercial structure, our deep-dive into dorsaVi’s modular ultra-edge commercialisation strategy covers the three-layer architecture separating sensing, compute, and memory into independently licensable modules, along with the dual pathway of direct embedding and foundry licensing.
CEO commentary
Mathew Regan, Group Chief Executive Officer of dorsaVi, addressed the significance of the milestone and the phase now underway.
Mathew Regan, Group Chief Executive Officer
“Completion of the CMOS front-end and middle-of-line fabrication is an important milestone, providing the physical foundation on which our proprietary RRAM technology can now be integrated.
The program now moves into the RRAM-specific back-end integration phase, ahead of electrical validation. We look forward to reporting against the next defined milestones as the program progresses.”
What investors should watch next
The program’s forward path is defined by a series of checkpoints rather than fixed guarantees. Per the Company, the next milestones include:
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Fabrication of dedicated BEOL integration structures
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RRAM stack deposition and cell etching
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Metal lines and interconnect fabrication
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Post-fabrication electrical validation of the wafer
Management stated it looks forward to “reporting against the next defined milestones as the program progresses.” Each of these steps brings dorsaVi closer to an electrically testable RRAM-CMOS chip and its broader low-power Physical AI hardware roadmap.
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