Adisyn Secures US Patent for Graphene Coating Tech Spanning Chips to Defence
Adisyn secures US patent protection for core graphene coating technology
Adisyn has received patent allowance from the United States Patent and Trademark Office (USPTO) for its proprietary graphene coating technology. US Patent No. 18/692,223, titled “Graphene Coated Metallic Surfaces, Devices and Method of Manufacture Thereof,” protects the company’s method of applying graphene coatings to metal surfaces, the resulting coated products, and devices incorporating these products.
The patent provides comprehensive intellectual property protection across the full value chain, from the manufacturing process through to commercial application. By securing protection in the United States, the world’s largest and most commercially significant patent market, Adisyn has established a defensible position for its graphene deposition technology across multiple high-value sectors.
The patented coating achieves a defect density of ≤10¹² defects/cm² with graphene coverage exceeding 90%. These specifications address critical performance thresholds required for semiconductor applications, where material quality directly impacts device reliability and electrical conductivity. The patent’s scope, covering both process and product claims, creates barriers to entry for competitors seeking to replicate Adisyn’s approach.
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What makes Adisyn’s graphene deposition method different
Conventional graphene deposition methods rely on high-temperature chemical vapour deposition (CVD) or catalytic metals that leave contaminating residues on the finished surface. These residues can compromise performance in sensitive applications such as semiconductor devices, where even trace contamination affects electrical properties and device reliability.
Adisyn’s patented approach enables graphene to be deposited on metal surfaces at low temperatures using specially designed molecular precursor compounds, categorised in the patent as Compounds A through F. The process produces high-quality graphene layers that are covalently bonded to the metal substrate, delivering superior adhesion and durability compared to physically deposited or weakly bonded alternatives.
The method supports multi-layer graphene coatings, with each successive graphene layer covalently bound to the layer below. This capability allows the company to tailor coating thickness and properties for specific applications without sacrificing bond strength or introducing defects. The deposition can be carried out via vacuum deposition techniques, including atomic layer deposition (ALD), which enables precision at the nanoscale.
Key technical characteristics of the patented coating include:
- Graphene defect density ≤10¹² defects/cm²
- Surface coverage >90%
- Covalent bonding between graphene and metal substrate
- Essentially free of catalytic metal residue
- Multi-layer capability with inter-layer covalent bonding
- Compatible with atomic layer deposition (ALD) for nanoscale precision
Why low defect density and high coverage matter for semiconductors
Defect density refers to the number of structural imperfections in the graphene layer per square centimetre. In semiconductor applications, these defects act as points where electrical resistance increases and current flow becomes less predictable. A defect density of ≤10¹² defects/cm² means the graphene layer maintains consistent electrical properties across the coated surface, which is essential for reliable device performance.
Surface coverage measures how completely the graphene layer coats the underlying metal. Coverage exceeding 90% ensures that the electrical and protective properties of the graphene extend uniformly across the substrate, preventing weak points or uncoated areas that could compromise device function.
These metrics are particularly significant in the context of advanced semiconductor manufacturing. As transistors shrink to smaller node sizes, copper interconnects face increasing performance limitations due to electron scattering and higher resistivity at nanoscale dimensions. Graphene’s superior electrical conductivity and atomic thinness position it as a potential replacement material for next-generation interconnects, where faster and more energy-efficient computing performance is required.
Commercial applications span semiconductors to defence
The patent covers applications across two strategic pillars: semiconductor and electronics applications, and defence and advanced materials applications. In the semiconductor vertical, protected uses include interconnects, back-end-of-line (BEOL) devices, nano-electromechanical devices, and graphene transistors. The electronics category extends to organic LEDs (OLEDs), transparent conductive electrodes, electro-optical sensors, and high-conductance interconnects.
Separately, the technology’s capability to produce high-quality graphene coatings on metal surfaces at low temperatures positions it for defence applications. Adisyn is developing graphene-enhanced composite materials to reduce the radar detectability of UAV and autonomous defence platforms through its subsidiary, 2D Radar Absorbers Ltd. The radar signature reduction programme represents a distinct commercialisation pathway where the same core deposition technology addresses a different market need.
| Application Category | Specific Applications |
|---|---|
| Semiconductor | Interconnects, BEOL devices, nano-electromechanical devices, graphene transistors |
| Electronics | OLEDs, transparent conductive electrodes, electro-optical sensors, high-conductance interconnects |
| Defence/Materials | Radar signature reduction composites (via 2D Radar Absorbers Ltd) |
The breadth of applications covered by the patent reflects the versatility of the underlying deposition method. By protecting the manufacturing process itself rather than a single end product, Adisyn has secured intellectual property that can support multiple revenue streams as different vertical markets mature.
Adisyn’s layered intellectual property strategy
The company’s intellectual property position extends beyond the granted patent through what management describes as a “blended protection strategy.” This approach combines registered patents with trade secrets, proprietary processes, and accumulated know-how developed over many years. While formal patent filings provide enforceable legal protection, some of the most valuable elements of the core technology will remain internal.
Trade secrets and operational expertise create a moat that is difficult to reverse-engineer, even for competitors with access to the published patent. The practical knowledge required to consistently achieve the specified defect density and coverage levels, the selection and handling of molecular precursor compounds, and the optimisation of deposition parameters represent proprietary capabilities that cannot be replicated simply by reading the patent claims.
Adisyn is evaluating additional patent filings in relevant jurisdictions to further strengthen its formal intellectual property portfolio. The company has indicated it will extend protection to markets where commercial opportunities align with strategic priorities, though some aspects of the technology will remain protected through confidentiality rather than public registration.
Managing Director commentary
Managing Director Arye Kohavi described the patent allowance as confirming the technology is “both novel and inventive,” representing a genuine scientific advance over existing approaches. He highlighted the patent’s broad coverage across the technology value chain, protecting not just the manufacturing method but also the graphene-coated metal products and devices that result from it.
Arye Kohavi, Managing Director
“The ability to deposit covalently bonded graphene at low temperatures, without catalytic metal residues, addresses real limitations that have constrained commercialisation of graphene coatings in semiconductors and advanced materials.”
Kohavi stated the patent positions Adisyn strongly as markets for graphene-based semiconductor and defence applications mature.
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Next steps for commercialisation
Adisyn is advancing commercialisation across both the semiconductor interconnect programme and the radar signature reduction vertical. The company is progressing engagement with potential partners and customers in both verticals, with intellectual property protection now secured in the United States providing a foundation for commercial discussions.
The company is also evaluating the extension of its intellectual property position through additional patent filings in relevant jurisdictions. Further updates on commercialisation progress and partner engagement will be provided as appropriate.
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