Independent expert takes Chipforge from written requirements to working FPGA hardware
An independent expert used the Chipforge platform to take written requirements through to working FPGA hardware, without assistance from the Chipforge team and without manual edits to the generated code. Pathkey.AI Ltd (ASX: PKY) confirmed the validation in an announcement on 4 November 2026.
An FPGA is a programmable chip, and the result moves Chipforge’s claims about its AI chip design platform closer to demonstrated capability. Key points from the announcement:
- Independent validation: the expert took written requirements to working FPGA hardware with no Chipforge team assistance and no manual code edits.
- CVDP benchmark: internal testing on NVIDIA’s public CVDP benchmark scored 14 to 28 percentage points higher than published results for GPT-5, Claude 4 Sonnet and the MAGE research agent on the same tasks.
- Release timing: Chipforge is in pre-production release, and the broader product release, Chipforge Studio, is targeted for Q1 2027.
- Tool chains: AMD Vivado and Altera Quartus workflows are complete, giving customers a choice of FPGA tool chains.
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What the independent evaluation showed
The evaluator and the result
Pathkey engaged Dr Smitha Kavallur Pisharath Gopi, a Senior Lecturer in the College of Computing and Data Science (CCDS) at Nanyang Technological University (NTU) in Singapore, to verify the platform’s ability to deliver working FPGA designs from written specifications. Her evaluation report, dated 23 October 2026, records successful implementation of a Digital Frequency Monitor and AES-128 encryption over UART on a Digilent Nexys A7-100T FPGA board.
The deal began as a binding option agreement funded from roughly $3.26 million in existing cash, with Chipforge’s exclusive licence from NTU’s Ntuitive vehicle forming the core of the intellectual property.
Dr Gopi entered the design problems as design intent. Chipforge planned the design, generated the chip code, built the tests, ran the simulations, revised the design where tests failed and produced the file that programs the chip.
The expert deployed the result to physical hardware, and it ran as specified. Where Dr Gopi wanted changes, she described them to the platform and the platform implemented them.
Scope of the evaluation
The evaluation covered the AMD Vivado workflow and assessed the agreed designs, rather than certifying the platform for every commercial application. Altera Quartus integration is also complete but was outside the scope of the evaluation.
Andrew Farnsworth, Pathkey Group CEO
“…All of that happened with no intervention or support from the Chipforge team, which is very encouraging to see.”
“We are now working with customers, and we are no longer just talking about what the platform will do. We can show them what it does, which is a huge step for us…”
FPGAs and Chipforge explained
An FPGA, short for field-programmable gate array, is a chip full of programmable logic that is already connected through a network of wiring. Loading a design sets what that logic does and how it is connected. The chip can then be wiped and loaded with another design.
Engineers can load a design, test it on the chip and change it without having to manufacture a new chip. Programmable chips can be used in finished products as well as to test designs before committing to custom silicon.
Designing custom hardware normally passes through several specialist steps, each with its own tools and people. Chipforge brings the work of designing a chip, testing it, fixing faults and preparing it to run on a chip into one platform.
An engineer sets the requirements and reviews the results. The platform generates the chip code, tests its behaviour and revises the design using test results and the engineer’s instructions. It then works with established chip-design tools to prepare the design for a programmable chip.
Keeping those steps within the platform is intended to reduce handovers and rework. For investors, that is the commercial pitch: less movement between specialist tools and people.
CVDP benchmark results beat published scores
Chipforge tested the platform internally on 262 problems across four categories in CVDP (Comprehensive Verilog Design Problems), NVIDIA’s public chip-design benchmark. The tasks involve creating a chip design from written requirements, completing unfinished code, modifying an existing design and fixing bugs.
The platform generates or edits the Verilog chip code and submits it to an open-source simulator, which runs the benchmark’s hidden tests. A problem passes only if every test passes, with no partial credit, human grading or AI self-assessment.
Chipforge’s scores were 14 to 28 percentage points above published results for GPT-5, Claude 4 Sonnet and the MAGE research agent on the same tasks. The debugging result represents 26 of 35 problems solved.
The comparison is not like for like. Chipforge’s results are first-pass, while the published results, drawn from NVIDIA ACE-RTL research, count a problem as solved if any of five attempts passes.
The company explains the approach this way: a general-purpose AI model writes code, but a mistake in chip code shows up only when the code is simulated or run on hardware. Chipforge adds engineering steps around the model, testing the code in a simulator, reading the failures, revising the design and testing again.
Several caveats apply:
- These are internal simulation results and have not been independently verified.
- They do not measure complete customer projects or operation on physical hardware.
- NVIDIA developed the benchmark but has not validated or endorsed Chipforge.
Customer projects will establish what the results mean for engineering time, cost and delivery.
From pilot to paid projects
Chipforge is in pre-production release and is delivering supported projects with its engineers. Customers can start with a specific design or fault, using Chipforge alongside their existing tools.
Initial engagements are fixed-price projects, with the scope, success criteria and engineering support agreed upfront. Successful delivery can lead to further projects, usage fees and software licences, with recurring revenue dependent on customers continuing to use the platform.
Chipforge’s first commercial contract is a ten-week proof-of-value program, and this first phase has been delivered. The next stage depends on the client being ready to integrate the work into its mechanical solution. This customer project is separate from the independent evaluation.
Management said it will be turning the capability into paid projects across Asia Pacific, including Singapore, Malaysia, Vietnam, Japan and Australia.
Roadmap and Performance Rights vesting
The company outlined the following development priorities:
- Chipforge Studio: the team is completing the initial release of the software engineers will use to access the platform, including testing, customer access, documentation and making it easier to get started.
- Tool support: current support includes AMD Vivado and Altera Quartus, with Lattice and Microchip support next. Vendor references do not imply partnership or certification.
- ASIC support: Chipforge can already support parts of application-specific integrated circuit (ASIC) design and digital verification, while physical implementation and the handoff to manufacturing are still in development.
- AI model: Chipforge is fine tuning and training an AI model for chip design and verification.
- Customer environment: the company is developing the ability to run within the customer’s own computing environment.
Since the acquisition in June 2026, the AMD Vivado workflow has come to run from design intent through hardware code generation, testing and verification to the file that programs the FPGA. Altera Quartus integration is complete, and the production environment has software release controls, performance monitoring and alerts.
The independent verification satisfies the vesting condition for 74,999,997 Class A Vendor Performance Rights and 13,500,000 Class C Incentive Performance Rights. The rights were issued pursuant to the acquisition of Chipforge Pte Ltd, first announced on 29 April 2026, with shareholder approval provided at the General Meeting held on 17 June 2026.
What happens next for Chipforge
The announcement points to three items ahead:
- Chipforge Studio release: targeted for Q1 2027, giving engineers access to the platform.
- Lattice and Microchip tool support: described as next, with no date given.
- Next stage of the first commercial contract: dependent on the client being ready to integrate the work into its mechanical solution, with no date given.
Pathkey said commercial progress will be measured through further paid engagements, work accepted by customers and repeat platform use. Product development and customer adoption remain subject to technical results, commercial terms and available resources.
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